吳永俊 Yung-Chun Wu

著作目錄(101_c302) 編於 2012/10/16
(*通訊作者) International Journals: (2010 SCI Impact factor, N/M)

  1. Hung-Bin Chen, Yung-Chun Wu, Chun-Yen Chang, Ming-Hung Han, Nan-Heng Lu, and Ya-Chi Cheng,“Performance of GAA poly-Si Nanosheet (2nm) channel of Junctionless Transistors with ideal Subthreshold Slope”International Symposium on VLSI Technology, 2013.

  2. Yung-Chun Wu, Ting-Chang Chang , Po-Tsun Liu, Chi-Shen Chen, Chun-Hao Tu, Hsiao-Wen Zan, Ya-Hsiang Tai, and Chun-Yen Chang, “High-Performance Polycrystalline Silicon Thin-Film Transistor with Multiple Nano-Wire Channels and Lightly-Doped Drain Structure” Appl. Phys. Lett. (SCI IF = 3.820, 14/116), vol. 84, no. 19,, pp. 3822-3824, 2004.

  3. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Yuan-Chun Wu, Cheng-Wei Chou, Chun-Hao Tu, Jen-Chung Lou, Chun-Yen Chang “Mobility Enhancement of Polysilicon Thin-Film Transistor using Nanowire Channels by Pattern- dependent Metal-Induced Lateral Crystallization” Appl. Phys. Lett. (SCI IF = 3.820, 14/116), 87, pp. 143504, 2005.

  4. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Chang-Wei Chou, Yuan-Chun Wu, Chun-Hao Tu, and Chun-Yen Chang, “Reduction of Leakage Current in Metal-Induced Lateral Crystallization Polysilicon Thin-Film Transistors with Dual-Gate and Multiple Nanowire Channels”, IEEE Electron Device Lett. (SCI IF = 2.714, 14/247), vol. 26, no. 9, pp. 646-648, 2005.

  5. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Chi-Shen Chen, Chun-Hao Tu, Hsiao-Wen Zan, Ya-Hsiang Tai, Chun-Yen Chang, “Effects of Channel Width on Electrical Characteristics of Polysilicon Thin-Film Transistors with Multiple Nanowire Channels” IEEE Trans. Electron Device, (SCI IF = 2.267, 34/247), vol. 52, no. 10, pp. 2343– 2346, Oct. 2005.
  6. Yung-Chun Wu, Ting-Chang Chang, Po-Tsun Liu, Cheng-Wei Chou, Yuan-Chun Wu, Chun-Hao Tu, and Chun-Yen Chang, “High performance Metal-induced Lateral Crystallization Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels and Multiple Gates” IEEE Trans. Nanotechnology (IF = 1.864, 50/247), vol. 5, no. 3, pp. 157-162, May,2006.

  7. Yung-Chun Wu, Ting-Chang Chang, Cheng-Wei Chou, Yuan-Chun Wu, Po-Tsun Liu, Chun-Hao Tu, Jen-Chung Lou, Chun-Yen Chang “Effects of Channel Width and NH3 Plasma Passivation on Electrical Characteristics of Polysilicon Thin-Film Transistorsby Pattern-Dependent Metal-Induced Lateral Crystallization”, Journal of The Electrochemical Society (SCI IF = 2.240, 1/18), 152, G545-549, 2005.

  8. Shu-Fen Hu, Yung-Chun Wu, Chin-Lung Sung, Chun-Yen Chang, Member, IEEE, and Tiao-Yuan Huang, “A Dual-Gate-Controlled Single-Electron Transistor Using Self-Aligned Polysilicon Sidewall Spacer Gates on Silicon-on-Insulator Nanowire” IEEE Trans. Nanotechnology (IF = 1.864, 50/247), vol.3, no. 1, pp.93-97, March, 2004.
  9. Shu-Fen Hu, Wei-Zhe Wong, Shiue-Shin Liu, Yung-Chun Wu, Chin-Lung Sung, Tiao-Yuan Huang, and Tzong-Jer Yang, “A Silicon Nanowire with a Coulomb Blockage Effect at Room Temperature”, Advanced Materials (SCI IF = 10.857, 7/222), vol. 14, no. 10, pp. 736-739, 2002.

  10. Chun-Hao Tu, Ting-Chang Chang, Po-Tsun Liu, Hsiao-Wen Zan, Ya-Hsiang Tai, Li-Wei Feng, Yung-Chun Wu, and Chun-Yen Chang, “Improvement of Reliability for Polycrystalline Thin-Film Transistors Using Self-Aligned Fluorinated Silica Glass Spacers”, Electrochem. Solid-State Lett. (SCI IF = 1.967, 26/222) 8, G209, 2005.

  11. Chun-Hao Tu, Ting-Chang Chang, Po-Tsun Liu, Hsiao-Wen Zan, Ya-Hsiang Tai, Che-Yu Yang, Yung-Chun Wu, Hsin-Chou Liu, Wei-Ren Chen, and Chun-Yen Chang, “Enhanced Performance of Poly-Si Thin Film Transistors Using Fluorine Ions Implantation”, Electrochem. Solid-State Lett. (SCI IF = 1.967, 26/222), 8, G246, 2005.

  12. Chun-Hao Tu, Ting-Chang Chang, Po-Tsun Liu, Chih-Hung Chen, Che-Yu Yang, Yung-Chun Wu, Hsin-Chou Liu, Li-Ting Chang, Chia-Chou Tsai, Simon M. Sze, and Chun-Yen Chang, “Electrical Enhancement of Solid Phase Crystallized Poly-Si Thin-Film Transistors with Fluorine Ion Implantation”, Journal of The Electrochemical Society (SCI IF = 2.240, 1/18), Volume 153, Issue 9, pp. G815-G818 2006.

  13. Chun-Hao Tu, Ting-Chang Chang, Po-Tsun Liu, Che-Yu Yang, Hsin-Chou Liu, Wei-Ren Chen, Yung-Chun Wu, Chun-Yen Chang, “Improvement of electrical characteristics for fluorine- ion-implanted poly-Si TFTs using ELC”, IEEE Electron Device Lett. (SCI IF = 2.714, 14/247), vol. 27, no. 4, pp. 262-264, 2006.
  14. Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Y.C. Wu, C.C. Tsai, T.S. Chang, Chen-Hsin Lien, “High-performance polycrystalline silicon thin-film transistors with oxide–nitride–oxide gate dielectric and multiple nanowire channels” Thin Solid Films, (SCI IF = 1.909, 3/18), 515 pp. 1112–1116, 2006.

  15. S. C. Chen, T. C. Chang, P. T. Liu, Y. C. Wu, P. H. Yen , C. F. Weng, Simon M. Sze, C. Y. Chang, C. H. Lien “Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels” Appl. Phys. Lett. (SCI IF = 3.820, 14/116), vol. 90, pp. 122111, 2007.

  16. Chun-Hao Tu, Ting-Chang Chang, Po-Tsun Liu, Che-Yu Yang, Student Member, IEEE, Li-Wei Feng, Chia-Chou Tsai, Li-Ting Chang, Yung-Chun Wu, Simon M. Sze, Chun-Yen Chang, “Improved Performance of F-Ions-Implanted Poly-Si Thin-Film Transistors Using Solid Phase Crystallization and Excimer Laser Crystallization”, Journal of Display Technology, (SCI IF = 1.674, 61/247), Vol. 3, No. 1, pp. 45-50, 2007.

  17. Yung-Chun Wu*, Ting-Chang Chang, Po-Tsun Liu,c and Li-Wei Feng, Degradation Behaviors of Trigate Nanowires Poly-Si TFTs with NH3 Plasma Passivation under Hot-Carrier Stress, Electrochem. Solid-State Lett. (SCI IF = 1.967, 26/222), 10 (8), H235-H238 2007.

  18. Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, Po-Shun Lin, Bae-Heng Tseng, Jang-Hung Shy, S. M. Sze, Chun-Yen Chang, and Chen-Hsin Lien, “A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory”, IEEE Electron Device Lett. (SCI IF = 2.714, 14/247), vol. 28, no. 9, pp. 809-811, 2007.

  19. Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, Chin-Cheng Ko, Sidney Yang, Li-Wei Feng,S. M. Sze, Chun-Ten Chang, Chen-Hsin Lien, “Nonvolatile Si/SiO2 /SiN/SiO2 /Si type polycrystalline silicon thin-film-transistor memory with nanowire channels for improvement of erasing characteristics”, Appl. Phys. Lett. (SCI IF = 3.820, 14/116), 91, p.193103, 2007.

  20. Shih-Ching Chen, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, Chin-Cheng Ko, Sidney Yang, Li-Wei Feng,S. M. Sze, Chun-Ten Chang, Chen-Hsin Lien, “Pi-shape gate polycrystalline silicon thin-film transistor for nonvolatile memory applications”, Appl. Phys. Lett. (SCI IF = 3.820, 14/116), 93, p.213101, 2007.

  21. Yung-Chun Wu*, Min-Feng Hung, Chin-Wei Chang, and Po-Wen Su, “Two-bit effect of trigate nanowires polycrystalline silicon thin-film-transistor nonvolatile memory with oxide/nitride/oxide gate dielectrics”, Appl. Phys. Lett. (SCI IF = 3.820, 14/116), 92, 163506, 2008

  22. Yung-Chun Wu*, Po-Wen Su, Chin-Wei Chang, and Min-Feng Hung , “Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure”, IEEE Electron Device Lett. (SCI IF = 2.714, 14/247), vol 29, no.11, pp. 1226-1228, 2008.

  23. Lun-Jyun Chen, Yung-Chun Wu*, Ji-Hong Chiang, Min-Feng Hung, Chin-Wei Chang, and Po-Wen Su, "Polycrystalline Silicon Thin-Film Flash Memory with Pi-Gate structure and HfO2 charge trapping layer," Japanese Journal of Applied Physics (SCI IF =1.018, 75/116), 48, pp.120215, 2009.

  24. Lun-Jyun Chen, Yung-Chun Wu*, Tien-Chun Lin, Jyun-Yang Huang, Min-Feng Hung, Jiang-Hung Chen, and Chun-Yen Chang, “Poly-Si Nanowire Nonvolatile Memory with Nanocrystal Indium–Gallium–Zinc–Oxide Charge-Trapping Layer,” IEEE Electron Device Lett. (SCI IF = 2.714, 14/247), vol 31, no.12, pp. 1407-1409, 2010.

  25. Shih-Ching Chen, Ting-Chang Chang, Yung-Chun Wu, Jing-Yi Chin, Yong-En Syu, S.M. Sze, Chun-Yen Chang, Hsing-Hua Wu, Yi-Chan Chen, “Temperature-dependent memory characteristics of silicon–oxide–nitride–oxide–silicon thin-film-transistors”, Thin Solid Films, (SCI IF = 1.909, 3/18), vol. 518, pp. 3999–4002, 2010.
  26. Lun-Jyun Chen, Yung-Chun Wu*, Ji-Hong Chiang, Min-Feng Hung, Chin-Wei Chang, and Po-Wen Su, “Comprehensive study of Pi-Gate Nanowires Poly-Si TFT Nonvolatile Memory with an HfO2 Charge Trapping Layer,” IEEE Trans. Nanotechnology, (IF = 1.864, 50/247), vol. 10, No. 2, pp. 260-265, 2011.
  27. Yung-Chun Wu*, Min-Feng Hung, Po-Wen Su, “Improving the performance of nanowires polycrystalline silicon twin thin-film transistors nonvolatile memory by NH3 plasma passivation,” Journal of The Electrochemical Society (SCI IF = 2.240, 1/18), vol. 158, issue. 5, pp. H578-H582, 2011.
  28. Min-Feng Hung, Yung-Chun Wu*, and Zih-Yun Tang, “High-performance gate-all-around polycrystalline silicon nanowire with silicon nanocrystals nonvolatile memory,” App. Phys. Lett. (SCI IF = 3.820, 14/116), vol. 98, pp. 162108, 2011.

  29. Hung-Bin Chen, Yung-Chun Wu*, Chao-Kan Yang, Lun-Chun Chen, Ji-Hong Chiang, and Chun-Yen Chang, "Impacts of Poly-Si Nanowire Shape on Gate-All-Around Flash Memory with Hybrid Trap Layer," IEEE Electron Device Lett. (SCI IF = 2.714, 14/247), vol 32, no.10, pp. 11382-1384, 2011.

  30. Jing-Jye Chang, Kuei-Shu Chang-Liao, Tien-Ko Wang, Yung-Chun Wu, Kao-Chao Lin, Chia-Yu Chen, Yu-Mou Chen, Jen-Pei Tseng, Min-Feng Hung, “Electrical Degradation and Recovery of Low-Temperature Polycrystalline Silicon Thin-Film Transistors in Polycrystalline Silicon Plasma Process” IEEE TRANSACTIONS ON ELECTRON DEVICES, (SCI IF = 2.267, 34/247), VOL. 58, NO. 8 , pp. 2448-2455, 2011.
  31. Min-Feng Hung, Yung-Chun Wu*, Ji-Hong Chiang, Jiang-Hung Chen, Lun-Chun Chen, “Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with a Nitride Trapping Layer” Journal of Nanoscience and Nanotechnology (SCI IF = 1.351, 94/222), Vol. 11, pp. 1–5, 2011.
  32. Hung-Bin Chen, Yung-Chun Wu*, Lun-Chun Chen, Ji-Hong Chiang, Chao-Kan Yang, Chun-Yen Chang, “High Reliability Poly-Si Nanowire Flash Memory with Sinanocrystal Embedded Charge Trapping Layer”, IEEE Electron Device Lett. (SCI IF = 2.714, 14/24,), VOL. 33, NO. 4, pp. 537-539, APRIL 2012.

  33. Min-Feng Hung, Yung-Chun Wu*, and Jiang-Hung Chen, “2-bit operation based on modulated Fowler-Nordheim tunneling in charge-trapping flash memory cell”, Appl. Phys. Lett. 100, 052107 2012.

  34. Min-Feng Hung, Yung-Chun Wu*, Shun-Cheng Tien, and Jiang-Hung Chen, “Polycrystalline-Si TFT TANOS Flash Memory Cell With Si Nanocrystals for High Program/Erase Speed and Good Retention”, IEEE Electron Device Lett. (SCI IF = 2.714, 14/245,), VOL. 33, NO. 5, pp. 649-651, MAY 2012.

  35. Tzong-Han Tsai, Yung-Chun Wu* Shih-Sian Yang, and Chun-Hao Chen, “Optimization of Amorphous Si/Crystalline Si Heterojunction Solar Cells by BF2 Ion Implantation”, Japanese Journal of Applied Physics, 51, pp. 04DP07, 2012.

  36. Hsin-Hui Hu, Yong-Ren Jheng, Yung-Chun Wu*, Min-Feng Hung, and Guo-Wei Huang, “Low-Frequency Noise in SONOS-TFT With a Trigate Nanowire Structure Under Program/Erase Operation”, IEEE Electron Device Lett. (SCI IF = 2.714, 14/24,), VOL. 33, NO. 9, pp. 1276-1279, SEP., 2012.

  37. Min-Feng Hung, *Yung-Chun Wu, Tsung-Ming Tsai, and Jiang-Hung Chen, Yi-Ray Jhan," Enhancement of Two-Bit Performance of Dual Pi-gate Charge Trapping Layer Flash Memory," Applied Physics Express 5 (2012) 121801.

  38. Ming-Hung Han, Chun-Yen Chang, Life Fellow, IEEE, Yi-Ruei Jhan, Jia-Jiun Wu,Hung-Bin Chen, Ya-Chi Cheng, and Yung-Chun Wu*, “Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis”, IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 2, pp.157-159, FEBRUARY 2013.

  39. Ming-Hung Han, Chun-Yen Chang, Life Fellow, IEEE, Hung-Bin Chen,Jia-Jiun Wu, Ya-Chi Cheng, and Yung-Chun Wu*, “Performance Comparison Between Bulk and SOI Junctionless Transistors” IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 2, pp.169-17, FEBRUARY 2013

  40. Min-Feng Hung, Yung-Chun Wu*, Jiun-Jye Chang, and Kuei-Shu Chang-Liao, “Twin Thin-Film Transistor Nonvolatile Memory With an Indium–Gallium–Zinc–Oxide Floating Gate”, IEEE ELECTRON DEVICE LETTERS, VOL. 34, NO. 1, pp. 75-77, JANUARY 2013.

International conference:

  1. Yung-Chun Wu, Chun-Yen Chang, Ting-Chang Chang, Po-Tsun Liu, Chi-Shen Chen, Chun-Hao Tu, Hsiao-Wen Zan, Ya-Hsiang Tai, and Simon Min Sze,“High Performance and High Reliability Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels”, p. 777-780, 2004 International Electron Device Meeting (IEDM), San Francisco USA.
  2. Yung-Chun Wu, Yuan-Chun Wu, Cheng-Wei Chou, Chun-Hao Tu, Jen-Chung Lou, Ting-Chang Chang, Po-Tsun Liu, and Chun-Yen Chang “Mobility Enhancement of Pattern-dependent Metal-Induced Lateral Crystallization Polysilicon Thin-Film Transistors with different dimensions”, p. 268-271, 2005 Society for Information Display (SID), Boston, USA.
  3. Yung-Chun Wu, Che-Yu Yang, Chi-Shen Chen, Ting-Chang Chang, Po-Tsun Liu, and Chun-Yen Chang, “The Effects of Electrical Stress and Temperature on the Properties of Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels”, p. 151-154, 1st Internatioal TFT conference, Seoul, Korea, 2005.
  4. Yung-Chun Wu, Ting-Chang Chang, Cheng-Wei Chou, Yuan-Chun Wu, Chun-Hao Tu, Po-Tsun Liu, and Chun-Yen Chang, “High performance Metal-induced Lateral Crystallization Polysilicon Thin-Film Transistors with Multiple Nano-Wire Channels and Multiple Gates”, The 2005 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2005.
  5. Yung-Chun Wu, Hung-Bin Chen, Li-Wei Feng, Ting-Chang Chang, Po-Tsun Liu, Chun-Yen Chang, “Reliability Study on Tri-Gate Nanowires Poly-Si TFTs under DC and AC Hot-Carrier Stress” The 7th IEEE International Conference on Nanotechnology, Hong Kong. 2007
  6. Yung-Chun Wu, Po-Wen Su, Chin-Wei Chang, Min-Feng Hung, “Program/Erase Characteristics of Twin Poly-Si Thin Film Transistors EEPROM with Tri-Gate Nanowires structure” The 2008 Silicon Nanoelectronics Workshop (SNW), Hawaii, USA, 2008.
  7. Lun-Jyun Chen, Yung-Chun Wu*, Ji-Hong Chiang, Chin-Wei Chang, and Po-Wen Su, “Novel Nanowires Ω-Gate Poly-Si TFT Nonvolatile Memory with HfO2 Trapping Layer”, Silicon Nanoelectronics Workshop (SNW), June 13-14, 2009, Kyoto, Japan.
  8. Yung-Chun Wu*, Chien-Ting Chen, Chien-Chun Lin, Guo-chung Chi, “Characterization of dye-sensitized solar cells with sputtered various metallic thin films on photoelectrode” TACT 2009 International Thin Films Conference (TACT 2009). December 14 - 16, 2009 , Taipei, Taiwan.
  9. Yung-Chun Wu*, Ji-Hong Chiang, , Lun-Jyun Chen *Hung-Bin Chen Po-Wen Su, Chin-Wei ChangTwin Poly-Si Thin Film Transistors EEPROM with Nitride Trapping Layer, International Display Manufacturing Conference & Exhibition (IDMC), April 27-30, 2009, Taipei, Taiwan.
  10. Yung-Chun Wu*, Min-Feng Hung, Ji-Hong Chiang, Jiang-Hung Chen, Lun-Chun Chen, “Fabrication and Characterization of Twin Poly-Si Thin Film Transistors EEPROM with Nitride Trapping Layer” IEEE International NanoElectronics Conference (INEC) January 3-8, 2010, Hong Kong, China
  11. Min-Feng Hung, Jiang-Hung Chen, and Yung-Chun Wu*,“Pi-Gate Nanowires TANOS Poly-Si TFT Nonvolatile Memory“, Silicon Nanoelectronics Workshop (SNW) June 13-14 2010, Honolulu, USA.
  12. Chao-Kan Yang, Hung-Bin Chen, Ji-Hong Jiang, Yung-Chun Wu*, Chun-Yen Chang, “High Performance Poly-Si Thin-Film Nonvolatile Memory with Dual Gate-All-Around Structure and hybrid trapping layer“, Silicon Nanoelectronics Workshop (SNW) June 13-14 2010, Honolulu, USA.
  13. Yung-Chun Wu*, Min-Feng Hung , Jiang-Hung Chen, Lun-Chun Chen, and Ji-Hong Jiang, “High-k materials and poly-Si nanowires in nonvolatile memory for 3D flash memory and display panel applications” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, June 30 – July 2, 2010, Tokyo, Japan. (Invited talk)


專利:

  1. 專利編號200612560，薄膜電晶體及其製造方法 THIN FILM TRANSISTOR AND FABRICATING METHOD THEREOF，張鼎張 TING-CHANG CHANG ;吳永俊 YUNG-CHUN WU ;劉柏村 PO-TSUN LIU ;張俊彥 CHUN-YEN CHANG，公開日期2006/04/16。

  2. 專利編號200622243，奈米生化感測元件及其製造方法 NANO-BIOCHEMICAL SENSOR AND ABRICATING METHOD THEREOF，張鼎張 CHANG, TING-CHANG ;王敏全 WANG, MING-CHAUNG ;劉柏村 LIU, PO-TSUN ;吳永俊 WU, YUNG-CHUN ;陳紀文 CHEN, CHI-WEN ;戴亞翔 TAI, YA-HSIANG，公開日期 2006/07/01。

  3. 專利編號200701313，多晶矽薄膜電晶體及其製造方法 POLYSILICON THIN-FILM TRANSISTORS AND FABRICATING METHOD THEREOF，張鼎張 TING-CHANG CHANG ;劉柏村 PO-TSUN LIU ;吳永俊 YUNG-CHUN WU，公開日期 2007/01/01。

  4. 專利編號200810116，具非揮發性記憶功能之薄膜電晶體裝置 THIN FILM TRANSISTOR DEVICE WITH NONVOLATILE MEMORY FUNCTION，張鼎張 CHANG, TING CHANG ;陳世青 CHEN, SHIH CHING ;劉柏村 LIU, PO TSUN ;吳永俊 WU, YUNG CHUN，公開日期 2008/02/16。

  5. 專利編號421639，一種沈積奈米級金粒子的方法，胡淑芬 ;葉儒林 ;劉如熹 ;吳永俊 ;黃調元，公開日期 2001/02/11。

  6. 專利編號550797，自我對準之複晶矽間隙壁閘極之單電子電晶體結構及其製造方法，胡淑芬 ;吳永俊 ;盧文泰 ;劉學欣 ;黃調元 ;趙天生，公開日期 2003/09/01。

  7. 專利編號I279840，多晶矽薄膜電晶體及其製造方法 POLYSILICON THIN-FILM TRANSISTORS AND FABRICATING METHOD THEREOF，張鼎張 CHANG, TING CHANG ;劉柏村 LIU, PO TSUN ;吳永俊 WU, YUNG CHUN，公開日期 2007/04/21。

  8. 專利編號I293685，奈米生化感測元件及其製造方法 NANO-BIOCHEMICAL SENSOR AND FABRICATING METHOD THEREOF，張鼎張 CHANG, TING CHANG ;王敏全 WANG, MING CHAUNG ;劉柏村 LIU, PO TSUN ;吳永俊 WU, YUNG CHUN ;陳紀文 CHEN, CHI WEN ;戴亞翔 TAI, YA HSIANG，公開日期 2008/02/21。

*** 大家可以上去看最新的impact factor & M/N

方法一：

進入下列網址

http://admin-pps.isiknowledge.com/JCR/JCR?PointOfEntry=Home&SID=R17Apk3B6n@ediFihdJ

選 Select an option: --> View all journals ， 找到 APL

期刊排名百分比 M/N


(下方) Journal Rank in Categories: -->選 Journal ranking。

方法二： 找到 APL 的ISSN 號碼 再用ISSN 來搜尋