Yung-Hsien Wu (巫勇賢) was born in Taipei in 1974. He received the B.S. from E.E. Dept., National Tsing Hua University (NTHU), Hsinchu, Taiwan, in 1996, and the Ph.D. degree in electronics engineering from the National Chiao-Tung University (NCTU), Hsinchu, Taiwan, in 2000. The subject of his Ph.D. dissertation was "Epitaxial SiGe Alloy Growth and Its Applications to Device".
During his research period in the institute, he was engaged in the development of deep sub-micron semiconductor device technology including high dielectric constant layer as alternative gate insulating material, gate oxide reliability issue, SiGe epitaxial layer as a channel for high speed transistor and SOI process for low power consumption applications, etc. And further, he was also active in the research and development of RF active and passive device design and characterization.
After graduating from NCTU, he joined ProMOS Technologies under the Defense Industry Reserve Duty System (DIRS, 國防工業訓儲制度) where he was engaged in advanced process development and assessment in Diffusion Department with major focus on 140/120 nm 256M DDR DRAM and 180 nm Flash memory. From 2000-2003, he was with furnace section and Dielectric-CVD section and responsible for process development, excursion prevention, yield enhancement, and integration of newly developed process into incumbent product. During this period, some systems were also established to reinforce process stability. In addition, he also led 120 nm DRAM and 180 nm Flash memory project in Diffusion Department by organizing and allocating all the resources and pondering the methods to overcome difficulties. Since the end of 2003, he has with Product Development Department where he was involved in the design debug of 110 nm 512M DDR2 DRAM products and the introduction of DDR2 product into mass production. He has authored or co-authored 7 technical papers and has been granted 19 patents in his professional field in ProMOS Technologies. Worth to be noticed is that abundant contribution in patent proposal earned him the individual IP award in 2002 and 2003.
In 2005, he joined the Department of Engineering and System Science, National Tsing Hua University, as an Assistant Professor. He was promoted to Associate Professor and Professor in 2009 and 2012 respectively. He was the recipient of the Young Faculty Research Award of National Tsing Hua University in 2010. He was also bestowed the Excellent Teaching Award and Outstanding Mentor Award by National Tsing Hua University in 2011. During Jun. to Sept. 2012, he was a visiting professor in Interuniversity Microelectronics Centre (IMEC), Belgium where he involved in the development of next-generation non-volatile memory technology.
His current area of research interests include
(1) Fabrication of high-performance Ge-based devices on Si substrate
(2) Research on crystalline high-κ dielectric for Si-based devices
(3) Development of high density MIM (metal-insulator-metal) capacitors
(4) Process development of high-efficiency Si-based solar cells
In general, the uniqueness of his research directions lies in (1) Development of Ge-based devices on Si substrate and (2) Research on crystalline high-permittivity (high-κ) dielectrics for electronic devices. For Ge-based devices on Si substrate, although some accomplishments have been achieved by many research groups, most of their studies are not compatible with incumbent ultra-large-scale integration (ULSI) technology because of the complex process, unstable process control or high cost. The main achievement of his research team is to successfully develop a simplified process which is compatible with existent ULSI technology to form an epitaxial Ge layer on Si substrate. Most importantly, based on the high quality of the thin Ge layer, high-performance Ge MOS capacitors, Ge MOSFETs and Ge nonvolatile memory devices have been realized, and these devices verify the feasibility and foresightedness of the process. Worth to be mentioned is that his research team has developed the world’s first Ge-channel charge trap flash memory devices on Si substrate in 2009 and first resistive random access memory (ReRAM) on Ge layer in 2011. Besides the common applications to optoelectronic and CMOS devices, the advent of these Ge-based nonvolatile memory devices ushers in a new research era for Ge technologies.
On the other hand, for the research on high-κ dielectrics, nevertheless related studies have been intensively reported in the literature, most studies focus on the application of amorphous high-κ dielectrics and the main reason is the issue of leakage current. However, the κ values of amorphous dielectrics rarely exceed 30 which limits their further applications. To pursue devices with higher performance, it is imperative to develop a next-generation dielectric with a higher κ value and lower leakage current. Based on the pursuit, his research team enthusiastically devotes to the development of crystalline dielectrics which can possess a κ value higher than 30. Take ZrO2 for example, it exists in three polymorphs which includes monoclinic, tetragonal, and cubic phase. Among these three phases, tetragonal ZrO2 enjoys the highest theoretical κ value of ~47 and it is very beneficial for aggressively scaled MOS devices to achieve a smaller equivalent oxide thickness (EOT). Furthermore, compared to its amorphous counterpart, a crystalline dielectric may have a slightly higher bandgap which is helpful in suppressing leakage current. For the past three years, more and more internationally renowned research groups engage in the field of crystalline high-κ dielectrics, and the physical properties and theoretical calculation for crystalline high-κ dielectrics have been exhaustively examined. However, discussion on their applications for electronic devices has been scarcely reported. Even for those discussing the applications for gate dielectrics, the adverse effects of grain boundaries in crystalline dielectrics on electrical characteristics such as leakage current has never been addressed. The major accomplishment of his research team for this field is to propose a novel approach to passivate grain boundaries related defects and confirm the effectiveness of this approach to suppress the leakage current without sacrificing its high κ value. This passivation process overcomes the intrinsic issue that has restricted the application of crystalline dielectrics for many years and paves a new avenue for the fulfillment of high-performance gate dielectrics. In addition, his research team also successfully masters the technology to control the concentration of oxygen vacancies in the crystalline high-κ dielectrics by modulating process parameters. Dielectrics with low and high concentration of oxygen vacancies can be respectively applied to gate dielectrics for MOS devices and charge trapping layer for flash memory devices. They are one of the pioneering research teams in the world focusing on the application of crystalline high-κ dielectrics to electronic devices.
Besides the issue of leakage current, another problem for crystalline dielectrics is the high stabilization temperature. Take ZrO2 for example, its tetragonal and cubic phase can be respectively stabilized above 1170 and 2297 oC which is not practical for ULSI technology. Fortunately, by reducing crystallite size, a tetragonal ZrO2 film can be formed by atomic layer deposition (ALD) at 350 oC and has been employed in gate dielectrics of MOS devices. In addition to ALD process, the stabilization temperature can also be lowered by doping Ge, Ce, Si, Ti, Y, or La into ZrO2 by co-evaporation or co-sputtering process. Although promising performance is observed, controlling the composition of the dielectric is not an easy task since the precise deposition rate of both sources should be maintained. Aiming at this process issue, his research team proposes a laminate structure which consists of ZrO2/dopant/ZrO2 to form a doped dielectric during subsequent annealing. This laminate structure provides a more reliable approach to control the dopant concentration because only the thickness ratio of each layer in the laminate needs to be controlled. His research team has successfully demonstrated the feasibility of crystalline high-κ dielectrics formed by the approach for MIM capacitors and MOS capacitors. More importantly, his research team has shown the world’s first flash memory devices that employ a crystalline high-κ dielectric as the charge trapping layer and it is expected that crystalline high-κ dielectrics hold great potential to be applied to many fields. Based on the abundant research achievements and profound foundation for Ge devices and crystalline high-κ dielectrics, his research team will desperately integrate these two technologies in the next few years to realize green devices with more competitive advantages.